モーデックでは商業活動に加えて、半導体関連技術向上に貢献すべく、学術研究活動もしております。

2012

Hitoshi Aoki and Masanori Shimasue, “Self-Heating characterization of Multi-Finger MOSFETs used for RF-CMOS applications” IET 2012.

2012

Hitoshi Aoki and Akira Matsuzawa, “n-Channel Metal-Oxide Semiconductor Field-Effect Transistor Modeling in Forward Body Bias Condition for Low Voltage Complementary Metal-Oxide-Semiconductor Circuits Design” Jpn. J. Appl. Phys. 51 (2012) 044301.

2010.09

Hitoshi Aoki,Masanori Shimasue, Masaya Miyahara,and Akira Matsuzawa “A Forward Body Bias Characterization for Low Voltage CMOS Circuits”, IEEE SSDM Sep.2010.

2008

Dongxu Yang, Li Zhang, Yan Wang, Zhiping Yu, Masanori Shimasue, Hitoshi Aoki, “An Efficient Compact Model for LDMOS with Self-Heating Effects,” ICSICT 2008.

2007.12

Ximeng Guan, Ming Zhang, Qiang Liu, and Zhiping Yu, “Simulation lnvestigation of Double-Gate CNR-MOSFETs with a Fully Self-Consistent NEGF and TB Method,” to be presented in lEDM, Washington DC, Dec. 2007.

2007

Hitoshi Aoki, “最新MOSFETデバイスモデリングとシミュレーション,” 電子情報通信学会誌, vol. 90, no. 2, 2007.

2007.01

Lu Gan, Zuochang Ye, Chao Jiao, and Zhiping Yu, “Macro-Modeling of NQS using Model-Order-Redudon(MOR)for Nonlinear Systems,” 4th lnt'l Workshop on Compact Modeling(IWCM)Yokohama, Japan, Jan. 2007.

2006.09

Hitoshi Aoki and Masanori Shimasue, “Gate Capacitance Analysis of Mulri-finger MOSFETs for RF Applications” IEEE SSDM Sep. 2006.

2004.07

Hitoshi Aoki, “Leaky Large Area Gate Capacitance Extraction for Nanometer CMOS Technology Used for RF Applications,” lnvited for Paper Presentation at the section of CMOS Modeling and Parameter Extraction, IMFEDK(lnternational Meeting for Future of Electron Devices, Kansai)2004, July 2004.

2004.06

Masanori Shimasue, Yasuo Kawahara, and Hitoshi Aoki, “Gate-to-Bulk Overlap Capacitance Extraction and Circuit Verification,” IEICE Trans. Electronics vol.E87-C, no.6, pp. 929-932, Jun. 2004.

2004.03

Masanori Shimasue, Yasuo Kawahara, and Hitoshi Aoki, “An Accurate Measurement and Extraction Method of Gate to Substrate Overlap Capacitance,” Proc. IEEE 2004 Int. Conference on Microelectronic Test Structures, pp. 293-296, March 2004.

2004.01

Masanori Shimasue and Hitoshi Aoki, “Practical Design and Modeling Procedure of Test Structures for Microwave Bare-Chip Devices,” IEICE Trans. Electronics, vol. E87-C no.1 pp.60-65 Jan. 2004

2002

Masanori Shimasue, Yasuo Kawahara, and Hitoshi Aoki, “A Novel Diffusion Capacitance Characterization Technique for the Parasitic BJT in PD SOI MOSFET's,” IEEE SSDM 2002.

2002.02

Hitoshi Aoki, “Bias and Geometry Dependent Flicker Noise Characterization for n-MOSFET's,” IEICE Trans. Electronics, vol. E85-C, no. 2, pp. 408-414, Feb. 2002.

2001.03

Hitoshi Aoki and Masanori Shimasue, “Channel Width and Length Dependent Flicker Noise Characterization for n-MOSFETs,” Proc. IEEE 2001 Int. Conference on Microelectronic Test Structures, vol. 14, Mar. 2001.

2001.03

Hitoshi Aoki, “Model Parameter Extractions for Recent CMOS Devices,” Tutorial Short Course, IEEE 2001 Int. Conference on Micrroelectronic Test Structures, Mar. 2001.

1999.06

Hitoshi Aoki and Zhiping Yu, “A TFT-LCD Simulation Method using Pixel MacroModels,” IEICE Trans. Electronics, vol.E82-C, no. 6, pp. 1025-1030, Jun. 1999.

1999.06

Hitoshi Aoki and Masanori Shimasue, “Noise Characterization of MOSFETs for RF Oscillator Design,” Proc. 1999 IEEE MTT-S International Microwave Symposium, Jun. 1999.

1999.05

Hitoshi Aoki, “Timing Measurement and Simulation of a TFT-LCD Panel Using Pixel Macro Models,” Proc. SID '99, May 1999.

1999

嶌末政憲, 青木均, “MOSFETの1/f 雑音測定とモデリング,” 信学論(C-II) ,vol. J82-C-II, no. 7, pp. 385-391, 1999.

1999.05

青木均, “a-Si TFTのフリッカーノイズ測定とモデリング,” 信学諭(C-I, II),vol. J82-C-II, no. 5, pp. 284-285, May 1999.

1998.03

Rajesh R. Divecha, Brian E. Stine, Duane O. Ouma, Eric C. Chang, Duane S. Boning, James E. Chung, Osamu S. Nakagawa, Hitoshi Aoki, Gary Ray, Donald Bradbury, and Soo-Young Oh, “Novel Statistical Metrology Framework for ldentifying Sources of Variation in Oxide Chemical-Mechanical Polishing,” J. Electrochem. Soc., vol. 145, no. 3, pp.1052-1059, Mar. 1998.

1997.03

James C. Chen, Dennis Sylvester, Chenming Hu, Hitoshi Aoki, Sam Nakagawa, and Soo-Young 0h, “An On-Chip, lnterconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution,” Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, vol. 10, Mar. 1997.

1996.01

Hitoshi Aoki, “Dynamic Characterization of a-Si TFT-LCD Pixels,” IEEE Trans. Electron Devices, vol. 43, no. 1, pp. 31-39, Jan. 1996.

1995

Peter M. O' Neill, Peter George, and Hitoshi Aoki, “A Complete CMOS SPICE Model Generation System,” Proc. HP Design Technology Conference, 1995.

1994

Hitoshi Aoki and Peter M. O' Neill, “CMOS Dynamic Characterization Using A Ring Oscillator,” Proc. SEMATECH Compact Modeling Workshop, 1994.

1993

Hitoshi Aoki and Ebrahim Khalily, “A New Semi-Empirical Model for Amorphous Silicon Thin-Film-Transistors,” Proc. 1993 International Workshop On VLSI Process and Device Modeling(VPAD), IEEE.

1990.07

青木均, “パッケージトランジスタのSパラメータ測定,” 信学論(C-II), vol. J73-C-II, no. 7, pp.432-435, Jul. 1990.